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74ACT138 - 3 TO 8 LINE DECODER INVERTING

General Description

The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports.

It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP).

Key Features

  • s TTL-compatible inputs s A Ports have standard 4 mA totem pole outputs s Typical input hysteresis of 0.5V s B Port high drive source/sink capability of 14 mA s Bidirectional non-inverting buffers s Supports IEEE P1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals s B Port outputs in High Impedance mode during power down s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74ACT1284SC 74ACT1.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74ACT1284 IEEE 1284 Transceiver June 1996 Revised November 1999 74ACT1284 IEEE 1284 Transceiver General Description The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP). The HD (active HIGH) input pin enables the B Ports to switch from open Drain to a high drive totem pole output, capable of sourcing 14 mA on all seven buffers. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (active HIGH) enables data flow from A Ports to B Ports. DIR (active LOW) enables data flow from B Ports to A Ports.