Datasheet Details
| Part number | 74ACT174 |
|---|---|
| Manufacturer | STMicroelectronics |
| File Size | 86.89 KB |
| Description | HEX D-TYPE FLIP-FLOP |
| Datasheet | 74ACT174_STMicroelectronics.pdf |
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Overview: 74ACT174 HEX D-TYPE FLIP FLOP WITH CLEAR PRELIMINARY DATA s s s s s s s s s HIGH SPEED: fMAX = 200 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74ACT174B 74ACT174M TTL. Information signals applied to D inputs are transfered to the Q output on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independentelyof the other inputs . The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
| Part number | 74ACT174 |
|---|---|
| Manufacturer | STMicroelectronics |
| File Size | 86.89 KB |
| Description | HEX D-TYPE FLIP-FLOP |
| Datasheet | 74ACT174_STMicroelectronics.pdf |
|
|
|
The ACT174 is an high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
It is ideal for low power applications mantaining high speed operation similar to eqivalent Bipolar Schottky PIN CONNECTION AND IEC LOGIC SYMBOLS May 1997 1/10 74ACT174 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK GND VCC NAME AND F UNCTIO N Asyncronous Master Reset (Active LOW) Flip-Flop Outpus Data Inputs Clock Input (LOW-to-HIGH, Edge- Triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CL EAR L H H H X: Don’t Care O UTPUTS CLOCK X Q L L H Qn FUNCTION CLEAR D X L H X NO CHANGE LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 74ACT174 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Sup
| Part Number | Description |
|---|---|
| 74ACT10 | TRIPLE 3-INPUT NAND GATE |
| 74ACT11 | TRIPLE 3-INPUT AND GATE |
| 74ACT125 | QUAD BUS BUFFERS |
| 74ACT138 | 3 TO 8 LINE DECODER INVERTING |
| 74ACT14 | HEX SCHMITT INVERTER |
| 74ACT157 | QUAD 2 CHANNEL MULTIPLEXER |
| 74ACT158 | QUAD 2 CHANNEL MULTIPLEXER |
| 74ACT161 | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER |
| 74ACT16244 | 16-BIT BUS BUFFER |
| 74ACT163 | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER |