DESCRIPTION
Information signals applied to D inputs are transfered to the Q output on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independentely of the other inputs . The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS May 1999 1/11 74ACT273 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 SYMBOL CLEAR Q0 to Q7 D0 to D7 CLOCK NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outpus Data Inputs Clock Input (LOW-to-HIGH, EdgeTriggered) Ground (0V) Positive Supply Voltage 10 20 GND VCC TRUTH TABLE INPUTS CL EAR L H H H X:Don’t Care OUT PUT S CLO CK X Q L L H Qn F UNCTIO N CLEAR D X L H X NO CHANGE LOGI...
STMicroelectronics
