DESCRIPTION
PIN CONNECTION AND IEC LOGIC SYMBOLS April 1999 1/13 74ACT299 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 SYMBOL S0, S1 G1, G2 A/QA to H/QH QA’ to QH’ CLEAR SR CLOCK SL GND VCC NAME AND F UNCTION Mode Select Inputs 3 State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3 State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage TRUTH TABLE MO DE CLEAR INPUTS F UNCTIO N OUTPUT SELECTED CONTRO L S1 S0 G1* G2* H L X L L L H H H H X L L H H L L H X L L L L L L L X X L L L L L L L X CLO CK INPUTS/OUTPUTS SERIAL A/Q A H/Q H SL X X X X X X X X X X H L X SR X X X X H L X X X Z L L QA0 H L QBn QBn a Z L L QH0 QGn QGn H L h L L L QA0 H L QBn QBn a L L L QH0 QGn QGn H L h O UT PUT S QA’ QH’ Z CLEAR HOLD SHIFT...
STMicroelectronics
