DESCRIPTION
A signal on the D INPUT is transferred to the Q and Q OUTPUTS during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/12 74ACT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK NAME AND FUNCTION Asyncronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asyncronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage 4, 10 5, 9 6, 8 7 14 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC TRUTH TABLE INPUTS CLR L H L H H H X : Don’t Care OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q L L H H L Qn NO CHANGE CLEAR PRESET PR H L L H H H LOGIC DIAGRAM...
STMicroelectronics
