DESCRIPTION
Depending on with the logic level at J and K inputs, this device changes state on the negative going transition of clock pulse (CK). CLEAR (CLR) and PRESET (PR) are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC76 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 6 2, 7 3, 8 4, 9 SYMBOL 1CK, 2CK NAME AND FUNCTION 10, 14 11, 15 16, 12 13 5 Clock Input(HIGH to LOW edge triggered) 1PR, 2PR Set Inputs (Active LOW) Asynchronous Reset 1CLR, 2CLR Inputs (Active LOW) Data Inputs: Flip-Flop 1 1J, 2J and 2 Complement Flip-Flop 1Q, 2Q Outputs 1Q, 2Q True Flip-Flop Outputs Data Inputs: Flip-Flop 1 1K, 2K and 2 GND Ground (0V) Vcc Positive Supply Voltage TRUTH TABLE INPUTS CLR L H L H H H H H X : Don’t Care OUTPUTS FUNCTION K X X X L H L H X CK X X X Q L H H Qn L H Qn Qn Q...
STMicroelectronics
