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74LVC161284 Datasheet PDF

STMicroelectronics 74LVC161284

The 74LVC161284 contains eight high speed non inverting bidirectional buffers and eleven control/ status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer.
Part No. 74LVC161284
Datasheet 74LVC161284 Download
Manufacturer
STMicroelectronics
Description LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
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74LVC161284 datasheet page 1 preview

DESCRIPTION

The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. It is available in the commercial temperature range. May 2003 1/11 Datasheet pdf - 74LVC161284 LOGIC DIAGRAM NOTE A: NOTE B: The PMOS transistors prevent backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. The PMOS transistor prevents backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. PIN

DESCRIPTION

PIN No 1 2, 3, 4, 5, 6 8, 9, 11, 12, 13, 14, 16, 17 19 20, 21, 22, 23 24 25 29, 28, 27, 26 30 41, 40, 38, 37, 36, 35, 33, 32 47, 46, 45, 44, 43 48 10, 15, 34, 39 7, 18 31, 42 SYMBOL HD A9 to A13 A1 to A8 PLI A14 to A17 HLO HLI C14 to C17 PLO B1 to B8 Y9 to Y13 DIR GND VCC VCC/CABLE NAME AND FUNCTION High Drive Enable Input Side A...
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