74LVCZ161284A Datasheet PDF | STMicroelectronics

STMicroelectronics 74LVCZ161284A

The 74LVCZ161284A contains eight high speed non inverting bidirectional buffers and eleven control/status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer.

Part No.	74LVCZ161284A
Datasheet	74LVCZ161284A Download
Manufacturer	STMicroelectronics
Description	LOW VOLTAGE HIGH SPEED IEEE 1284 TRANSCEIVER
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DESCRIPTION

The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. The Y output (Y9-Y13) stay in the high state after power-on until an associated input A9-A13) goes high. When an associated input goes high, all Y outputs are active, and non July 2005 1/12 74LVCZ161284A inverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at LOGIC DIAGRAM power-on. It is available in the commercial temperature range. NOTE A: NOTE B: NOTE C: The PMOS transistors prevent backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. The PMOS transistor prevents backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND.