DESCRIPTION
cThe SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX08MTR 74LVX08TTR The internal circuit is composed of 2 stages including buffer output, which provides high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ObsoleteFigure 1: Pin Connection And IEC Logic Symbols August 2004 Rev. 4 1/11 74LVX08 Figure 2: Input Equivalent Circuit Table 2: Pin DESCRIPTION
PIN N° 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC NAME AND FUNCTION Data Inputs Data Inputs Data Outputs Ground (0V) Positive Supply Voltage Table 3: Truth Table roduct(s)Table 4: ABSOLUTE MAXIMUM RATINGS
ABY LLL LHL HL L HHH PSymbol Parameter teVCC...
STMicroelectronics
