DESCRIPTION
c On o the positive transition of the clock, the Q outputs bs will be set to the logic state that were setup at the SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74LVX574MTR 74LVX574TTR D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. O Figure 1: Pin Connection And IEC Logic Symbols August 2004 Rev.
STMicroelectronics
