DESCRIPTION
On the positive transition of the clock, the Q output will be set to the logic inverted state that was setup at the D input. SOT23-5L SOT323-5L ORDER CODES PACKAGE SOT23-5L SOT323-5L T&R 74V1G80STR 74V1G80CTR Following the hold time interval, data at the D input can be changed without affecting the level at the output. Power down protection is provided on input and 0 to 7V can be accepted on input with no regard to the supply voltage. This device can be used to interface 5V to 3V. It’s available in the commercial temperature range. All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2004 1/10 74V1G80 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN N° 1 2 4 3 5 SYMBOL D CK Q GND VCC NAME AND FUNCTION Data Input Clock Input (Positive Edge) Inverted Flip-Flop Output Ground (0V) Positive Supply Voltage TRUTH TABLE D CK Q L H H L L Qn H Qn ABSOLUTE MAX...
STMicroelectronics
