DESCRIPTION
On the positive transition of the (nCK), the nQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the 8 outputs (nQ) will be in a normal state (HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. February 2003 1/12 74VCXH16374 All inputs and outputs are equipped with protection circuits against static discharge, giving INPUT AND OUTPUT EQUIVALENT CIRCUIT them 2KV ESD immunity and transient excess voltage. PIN DESCRIPTION
PIN No 1 SYMBOL 1OE NAME AND FUNCTION IEC LOGIC SYMBOLS 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State...
STMicroelectronics
