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74VHC32
QUAD 2-INPUT OR GATE
PRELIMINARY DATA
s s
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HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 32 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHC32M 74VHC32T The internal circuit is composed of 2 stages including buffer output, which provide high noise immunity and stable output.