DESCRIPTION
On the positive transition of the clock, the Q outputs will be set to the logic state that were PIN CONNECTION AND IEC LOGIC SYMBOLS setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2000 1/10 74VHCT374A INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs CLOCK GND VCC Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positiv...
STMicroelectronics
