8S003K3
Description
12 4.1 Central processing unit STM8.
Key Features
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set Memories
- Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
- RAM: 1 Kbyte
- Data memory: 128 bytes true data EEPROM; endurance up to 100 k write/erase cycles Clock, reset and supply management
- 2.95 V to 5.5 V operating voltage
- Flexible clock control, 4 master clock sources
- Low-power crystal resonator oscillator - External clock input - Internal, user-trimmable 16 MHz RC - Internal low-power 128 kHz RC
- Clock security system with clock monitor
- Nested interrupt controller with 32 interrupts
