FEATURES
Super Harvard Architecture Computer (SHARC) 4 Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory, Integrated I/O Peripheral I 2S Support for 8 Simultaneous Receive and Transmit Channels 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory 2 External Port, DMA Channels and 8 Serial Port, DMA Channels Decodes Industry Standard Formats Using a 32-Bit Floating Point Implementation for Decoding Dolby® Digital AC-3, Dolby Digital EX Processing Dolby Pro Logic®, 96 kHz, Dolby Pro Logic II Dolby Headphone, Dolby 3/0 DTS® 5.1, DTS-ES®-Discreet 6.1, DTS Matrix and Matrix 3.0, DTS 96/24 ®, DTS NEO:6 THX ® Ultra, Select, Ultra2, 5.1, 7.1, EX SRS ® Labs Circle Surround II TM, Virtual Loudspeaker MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode PCM, PCM 96 kHz HDCD, MLP* Delay 7.1, 96 kHz Bass 7.1, 96 kHz, Bass/...
STMicroelectronics
