CR8F6123 Description
11 4.1 Central processing unit CR8F . 11 4.2 Single wire interface module (SWIM) and debug module (DM) . 12 4.3 Interrupt controller.
CR8F6123 Key Features
- 16 MHz advanced CR8Fcore with Harvard architecture and 3-stage pipeline
- Extended instruction set
- Program memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
- Data memory: 640 bytes true data EEPROM; endurance 300 kcycles
- RAM: 1 Kbytes
- 2.95 to 5.5 V operating voltage
- Flexible clock control, 4 master clock sources
- Low power crystal resonator oscillator
- External clock input
- Internal, user-trimmable 16 MHz RC