Datasheet4U Logo Datasheet4U.com

ESDALC6V1-5P6 - ESD protection

General Description

The ESDALC6V1-5P6 is a monolithic array designed to protect up to 5 lines against ESD transients.

The device is ideal for high speed interface applications where both reduced printed circuit board space and power absorption capability are required.

Key Features

  • Diode array topology Low capacitance (12 pF typical) Lead-free package SOT666 Benefits.
  • Low capacitance uni-directional ESD protection. Low PCB space consuming, 2.5 mm2 max. footprint Low leakage current High reliability offered by monolithic integration Figure 1. ESDALC6V1-5P6 functional diagram Complies with the following standards.
  • IEC 61000-4-2 level 4:.
  • 8 kV (contact discharge).
  • 15 kV (air discharge) MIL STD 883G-Method 30.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ESDALC6V1-5T6 TVS Clamping Arrays ST Microelectronics
ESDALC6V1-1BM2 TVS Diode Leiditech
ESDALC6V1-1BT2 Single line low capacitance Transil ST Microelectronics
ESDALC6V1-1BU2 Single-line low capacitance ST Microelectronics
ESDALC6V1-1U2 TVS Clamping Arrays ST Microelectronics

Other Datasheets by STMicroelectronics

Part Number Description
ESDALC6V1-5M6 (ESDALC6V1xxM6) 4 and 5 line low capacitance TRANSIL array
ESDALC6V1-1BM2 Single line low capacitance
ESDALC6V1-1M2 Single line low capacitance Transil
ESDALC6V1C2 Quad low capacitance TRANSIL array
ESDALC6V1F2 Quad low capacitance Transil array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com ESDALC6V1-5P6 ESD protection for high speed interface Features ■ ■ ■ Diode array topology Low capacitance (12 pF typical) Lead-free package SOT666 Benefits ■ ■ ■ ■ Low capacitance uni-directional ESD protection. Low PCB space consuming, 2.5 mm2 max. footprint Low leakage current High reliability offered by monolithic integration Figure 1.