DESCRIPTION
Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded A-law or µ–law PCM format. The decode portion of each device consists of an expanding decoder, which reconstructs the analog signal from the companded A-law or µ–law code, a low-pass filter which corrects for the sin x/x response of the decoder output and rejects signals above 3400 Hz and is followed by a single-ended power amplifier capable of driving low impedance loads. The devices require 1.536 MHz, 1.544 March 2000 DIP16 (Plastic) ORDERING NUMBERS: ETC5057N ETC5054N SO16 (Wide) ORDERING NUMBERS: ETC5057D ETC5054D PLCC20 ORDERING NUMBERS: ETC5057FN ETC5054FN MHz, or 2.048 MHz transmit and receive master clocks, which may be asynchronous, transmit and receive bit clocks which may vary from 64 kHz to 2.048 MHz, and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with both industry standard formats.
STMicroelectronics
