STMicroelectronics FC106
The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. The FC106 implements the Fibre Channel electrical transceiver physical layer specification for 1.0625 Gbit/s.| Part No. | FC106 |
|---|---|
| Datasheet | FC106 Download |
| Manufacturer |  STMicroelectronics |
| Description | Fibre Channel Transceiver |
| Buy | Stock & Price |
FEATURES
s Serial Link Transceiver q q serializer and deserializer implementing the Fibre Channel FC0 and FC1 layers Parallel Interface Receive Byte Clock REFCLK 10 bits s s s s Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X) Direct interfaces to optical tranceivers Plesiochronous mode operation q 8 bit / 10 bit DECODER (optional) 8 bit / 10 bit ENCODER (optional) transmitter and receiver clock frequencies may differ by up to 100 ppm DESER IALIZER CLOCK RECOVERY BYTE AND WORD ALIGNEMENT s s s s s s s s s s Integrated Fibre Channel 8b/10b encode/decode (optional use through JTAG) Byte and word synchronization of incoming serial stream Supports any DC-balanced encoding scheme Internal Loop-Back for Self-Test Random Pattern Auto-Test Optional integrated impedance adaptation to transmission line characteristics (50 or 75 ohms) TTL compatible parallel I/O’s JTAG Test Access Port 0.35 µ CMOS Technology for low cost an...
