DESCRIPTION
OF ”B” SERIES CMOS DEVICES” Whith JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided. EY (Plastic Package) F (Ceramic Frit Seal Package) M1 (Micro Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC4035BF HCF4035BM1 HCF4035BEY HCF4035BC1 DESCRIPTION
Register stages 2, 3, and 4 are coupled in a serial D flipflop configuration when the register is in the serial mode (PARALLEL/SERIAL control low). Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/COMPLEMENT control functions asynchronously with respect to the CLOCK signal. JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications.
STMicroelectronics
