HCC4724B
DESCRIPTION
OF ’ B ’ SERIES CMOS DEVICES ”
EY (Plastic Package)
F (Ceramic Package)
M1 (Micro Package)
C1 (Chip Carrier)
ORDER CODES : HCC4724BF HCF4724BM1 HCF4724BEY HCF4724BC1
APPLICATION MULTI-LINE DECODERS A/D CONVERTERS PIN CONNECTIONS DESCRIPTION
The HCC/HCF4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at low level. When WRITE DISABLE is high, data entry is inhibited however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic ” 0 ” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the...
