DESCRIPTION
OF B SERIES CMOS DEVICES" DESCRIPTION
CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4 or 2 counter configuration can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the data input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a HCF4011B gate DIP SOP ORDER CODES PACKAGE TUBE DIP SOP HCF4018BEY HCF4018BM1 T&R HCF4018M013TR package to properly gate the feedback connection to the DATA input. Divide-by-functions greater than 10 can be achieved by use of multiple HCF4018B units. The counter is advanced one count at the positive clock signalstransition. Schmitt trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESENT-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence. PIN CONN...
STMicroelectronics
