DESCRIPTION
OF ’ B ’ SERIES CMOS DEVICES ” EY (Plastic Package) F (Ceramic Package) M1 (Micro Package) C1 (Chip Carrier) ORDER CODES : HCC4724BF HCF4724BM1 HCF4724BEY HCF4724BC1 APPLICATION MULTI-LINE DECODERS A/D CONVERTERS PIN CONNECTIONS DESCRIPTION
Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at low level. A master RESET input is available, which resets all bits to a logic ” 0 ” level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic ” 0 ” level. September 1988 1/14 HCC/HCF4724B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATING Symbol VDD * Vi II Ptot Parameter Supply Voltage: HCC Types HCF Types Input Voltage DC Input Current (any one input) Total Power Dissipation (p...
STMicroelectronics
