STMicroelectronics IRF740S
This power MOSFET is designed using the company’s consolidated strip layout-based MESH OVERLAY™ process. This technology matches and improves the performances compared with standard parts from various sources.DESCRIPTION
APPLICATIONS
s HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s DC/DC COVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT. INTERNAL SCHEMATIC DIAGRAMABSOLUTE MAXIMUM RATINGS
Symbol V DS V DGR V GS ID ID IDM (● ) P t ot dv/dt( 1 ) T stg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k Ω ) Gate-source Voltage Drain Current (continuous) at Tc = 25 C Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) Total Dissipation at Tc = 25 C Derating F actor Peak Diode Recovery voltage slope Storage T emperature Max. O perating Junction Temperature o o o Value 400 400 ± 20 10 6.3 40 125 1.0 4.0 -65 to 150 150 (1) ISD ≤ 10 A, di/dt ≤120 Α/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Uni t V V V A A A W W/ C V/ ns o o o C C (●) Pulse width limited by safe operating area August 1998 1/8 IRF740S THERMAL DATA R t hj-ca se Rthj -amb R thc- si nk Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Cas...