L100NH3LL Datasheet | STMicroelectronics

Features Type VDSS RDS(on) max STL100NH3LL 30 V <0.0035 Ω 25A (1) t(s)1. The value is rated according Rthj-pcb c- Improved die-to-footprint ratio du- Very low profile package (1 mm max) ro )- Very low thermal resistance P t(s- Conduction losses reduced te c- Switching losses reduced sole rodu Application b P- Switching applications ) - O lete Description ct(s bso This series utilizes the last advanced design rules uof ST’s proprietary STrip FET™ technology. This d - Oprocess plete to unique metallization ro )technique realised the most advanced low voltage P t(s Power MOSFET in Power FLAT™(6x5). The chip- scaled Power FLAT™ package allows a significant lete ucboard space saving, still boosting the dperformance. Power FLAT™( 6x5 ) Figure 1. Internal schematic diagram Obso lete Pro Table 1. Device summary so Order code Ob STL100NH3LL Marking L100NH3LL Package...