M24M01-V Overview
AI04048B SDA M24M01 1 2 3 4 8 7 6 5 AI04051C VCC WC SCL SDA Table 1. Signal Names E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground Note: 1. DU = Don’t Use (should be left unconnected, or tied to VSS) These devices are patible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. Power On Reset: V CC Lock-Out Write Protect In order to...
M24M01-V Key Features
- 2.7V to 3.6V for M24M01-V
- 1.8V to 3.6V for M24M01-S
- the device will not respond to any mand. In the same way, when VCC drops from the operating voltage, below the POR thres
- tPU after V CC passed the Vth threshold
- VCC passed the VCC(m