M27V322 Datasheet | STMicroelectronics

e M27V322 is a 32 Mbit EPROM offered in the UV range (ultra violet erase) and OTP range. It is ideally suited for microprocessor systems requiring large data or program storage. It is organised as 2 MWords of 16 bit. The pin-out is patible with a 32 Mbit Mask ROM. The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V322 is offered in PDIP42 package. 21 A0-A20 16 Q0-Q15 E GVPP AI03050 March 2000 1/13 Figure 2A. DIP Connections A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS GVPP Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 42 2 41 3 40 4 39 5 38 6 37 7 36 35 8 9 34 10 33 M27V322 32 11 31 12 30 13 29 14 28 15 27 16 17 26 18 25 19 24 20 23 22 21 AI03051 Table 1. Signal Names A0-A20 Address Inputs Data Outputs Chip Enable Output Enable / Program Supply Supply Voltage Ground A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 A20 VSS Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q0-Q15 E GVPP VCC VSS DEVICE OPERATION The operating modes of the M27V322 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL patible except for V PP and 12V on A9 for the Electronic Signature. Read Mode The M27V322 has a word-wide organization. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the address access time (t AVQV) is equal to the delay from E to output (t ELQV). Data is available at the output after a delay of t GLQV from the falling edge of GVPP, assuming that E has been low and the addresses have been stable for at least t AVQVt GLQV. Standby Mode The M27V322...