DESCRIPTION
These electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits, and operate down to 2.7 V. These devices are available in Plastic Small Outline and Thin Shrink Small Outline packages. These devices are written by the ACR card-issuer, and then accessed in Read mode in the application, using the ACR Serial Bus protocol. The device behaves as a slave in the ACR Serial Bus protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition 8 1 TSSOP8 (DW) 169 mil width Figure 1. Logic Diagram VCC 3 E0-E2 SDA M34A02 Table 1. Signal Names E0, E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground SCL WC VSS AI03794 April 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/15 M34A02 Figure 2. SO and TSSOP Connections Figure 3.
STMicroelectronics
