DESCRIPTION
The M34C00 is a 384-bit serial EEPROM. Care must be taken when using this sequence as its effect cannot be reversed. The top third of the memory area (from location 20h to 2Fh) is already configured to give the functional equivalence of a non-erasable memory. That is, it is initialized to all 1s (FFh), and the user is able to reset any number of those 1s to 0; but there is no mechanism for the user to set a 0 back to a 1. The M34C00 is a 384-bit electrically erasable programmable memory (EEPROM), organized as 48 x 8 bits. Figure 1. Logic Diagram VCC SCL M34C00 SDA Table 1. Signal Names SDA SCL VCC VSS Serial Data Serial Clock Supply Voltage Ground VSS AI03394 August 2001 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/15 M34C00 Figure 2A. SO and TSSOP Connections When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
STMicroelectronics
