M48Z2M1V
Key Features
- Integrated, ultra low power SRAM, power-fail control circuit, and batteries
- Conventional SRAM operation; unlimited )WRITE cycles t(s
- 10 years of data retention in the absence of cpower du
- Automatic power-fail chip deselect and WRITE roprotection P
- Batteries are internally isolated until power is -applied t(s)
- Pin and function compatible with JEDEC standard 2 Mb x 8 SRAMs uc
