DESCRIPTION
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually (except Blocks 15 to 0, which have global protection) to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The M50LPW116 features an asymmetrical block architecture. It has an array of 50 blocks: 1 Boot Block of 16KBytes, 2 Parameter Blocks of VCC VPP 11 A0-A10 8 DQ0-DQ7 RC IC G W RP M50LPW116 RB VSS AI05468 Figure 3. TSOP Connections NC IC (VIH...
STMicroelectronics
