DESCRIPTION
Each counter is composed of a divide-by-two and divide-by-five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual biquinary, or various combinations up to a single divide-by-100 counter. Each 4-bit counter is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input. When clear is set low all four bits of each counter are set to low. This enables count truncation and allows the implementation of divide-by-N counter configurations. All inputs are equipped with protection circuits against static discharge and transient excess voltage. February 1993 NC = No Internal Con- 1/13 M54/M74HC390 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE OUTPUTS COUNT 0 1 2 3 4 5 6 7 8 9 QD L L L L L L L L H H INPUTS CLOCK A X X CLOCK B X X CLEAR H L L QA L BCD COUNT * QC L L L L H H H H L L QB L L H H L L H H L L QA L H L H L H L H L H QA L L L L L H H H H H BI-QUINARY ** QD L L L L H L L L...