DESCRIPTION
If the device is enabled, 3 binary select inputs (A, B and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs are equipped with protection circuits against static discharge and tran- sient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices 2 are designed to directly interface HSC MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. INPUT AND OUTPUT EQUIVALENT CIRCUIT ORDER CODES : M54HCT138F1R M74HCT138M1R M74HCT138B1R M74HCT138C1R PIN CONNECTIONS (top view) NC = No Internal Connection February 1993 1/10 M54/M74HCT138 TRUTH TABLE INPUTS E...
STMicroelectronics
