DESCRIPTION
On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs (HCT574) or their complements (HCT564). While the OE input is low, the eight outputs will be in a normal logic state (high or low logic level), and while high level, the outputs will be in a high impedance state. The output control does not affect the inPIN CONNECTION (top view) ternal operation of flip-flops. That is, the old data can be retained or the new data can be entered even while the outputs are off. The application engineer has a choice of combination of inverting and non-inverting outputs. The 3-state output configuration and the wide choice of outline make bus-organized systems simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices 2 are designed to directly interface HSC MOS systems with TTL and NMOS components.
STMicroelectronics
