DESCRIPTION
In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then re-protected. A parameter block "Security block" can be permanently protected against programming and erasing in order to increase the data security. An optional 12V VPP power supply is provided to speed up the program phase at costumer production. An internal command interface (C.I.) decodes the instructions to access/modify the memory content. The program/erase controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Two status registers indicate the state of each bank. Instructions for Read Array, Read Electronic Signature, Read Status Register, Clear Status Reg...
STMicroelectronics
