DESCRIPTION
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation allows maximum flexibility in timing. These devices allow data transmission from the A bus to B bus or from the B to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8bit codes appearing on the two sets of buses will be identical for the ’HC623 or complementary for the ’HC620. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
STMicroelectronics
