DESCRIPTION
Depending on with the logic level at the J and K inputs this device changes state on the negative going transition of the clock pulse. CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIVALENT CIRCUIT NC = No Internal Connection October 1992 1/11 M54/M74HC76 TRUTH TABLE INPUTS CLR L H L H H H H H X: Don’t Care OUTPUTS K X X X L H L H X CK X X X Q L H H Qn L H Qn Qn Q H L H Qn H L Qn Qn PR H L L H H H H H J X X X L L H H X FUNCTION CLEAR PRESET NO CHANGE TOGGLE NO CHANGE PIN DESCRIPTION
PIN No 1, 6 2, 7 3, 8 4, 9 10, 14 11, 15 16, 12 5 13 SYMBOL 1CK, 2CK 1PR, 2PR 1CLR, 2CLR 1J, 2J 1Q, 2Q 1Q, 2Q 1K, 2K GND V CC NAME AND FUNCTION Clock Input (HIGH to LOW edge triggered) Set Inputs (Active LOW) Asynchronous Reset Inputs (Active LOW) Data Inputs: Flip-Flop 1 and 2 Complem...
STMicroelectronics
