DESCRIPTION
Ithas the samehigh speed performance ofLSTTL combined with trueCMOSlow power consumption. When GLgoes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GLremains high no address changes will be recognized. Output enable pins G1 and G2, control the state of the outputs independently ofthe select orlatch-enable inputs. All theoutputs are high unless G1 is high and G2 is low. The HC137 is ideally suited for the implementation of glitch-free decoders in stored-address applications in bus oriented systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices aredesigned todirectly interfaceHSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. INPUT AND...
STMicroelectronics
