DESCRIPTION
These SPI-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M95256) and 16K x 8 bits (M95128), and operate down to 2.7 V (for the Figure 1. Logic Diagram VCC Table 1. Signal Names C D Q Serial Clock Serial Data Input Serial Data Output D C S W M95xxx Q S W HOLD VCC VSS Chip Select HOLD Write Protect Hold Supply Voltage Ground VSS AI01789C March 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/21 M95256, M95128 Figure 2A. DIP Connections Figure 2C. TSSOP Connections M95128 M95xxx S Q W VSS 1 2 3 4 8 7 6 5 AI01790C VCC HOLD C D S Q NC NC NC W VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 AI02346 VCC HOLD NC NC NC C D Note: 1. NC = Not Connected Figure 2B. SO Connections -V version), 2.5 V (for the -W version), and down to 1.8 V (for the -R version of each device). The device is selected when the chip select input (S) is held low. Communications with the chip can be interrupted using the hold input (HOLD).
STMicroelectronics
