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PSD913F2 - ISP Peripherals

General Description

10 Register Description and Address Offset 14 Functional Blocks 15 Memory Blocks 15 Main Flash and Secondary Flash Memory Description15 SRAM27 Memory Chip Selects 27 Page Register 30 PLDs

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Full PDF Text Transcription for PSD913F2 (Reference)

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PSD913F2 PSD934F2 PSD954F2 Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs PRELIMINARY DATA FEATURES SUMMARY s Single Supply Voltage: – 5 V±10% for PSD9xxF2...

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DATA FEATURES SUMMARY s Single Supply Voltage: – 5 V±10% for PSD9xxF2 – 3.3 V±10% for PSD9xxF2-V s Up to 2Mbit of Primary Flash Memory (8 uniform sectors) s 256Kbit Secondary Flash Memory (4 uniform sectors) s Up to 256Kbit SRAM s Over 2,000 Gates of PLD: DPLD s 27 Reconfigurable I/O ports s Enhanced JTAG Serial Port s Programmable power management s High Endurance: – 100,000 Erase/Write Cycles of Flash Memory – 1,000 Erase/Write Cycles of PLD Figure 1. Packages PQFP52 (T) PLCC52 (K) January 2002 1/3 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change

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