SPC564A80B4 Datasheet | STMicroelectronics

Features - 150 MHz e200z4 Power Architecture® core - Variable length instruction encoding (VLE) - Superscalar architecture with 2 execution units - Up to 2 integer or floating point instructions per cycle - Up to 4 multiply and accumulate operations per cycle - Memory organization - 4 MB on-chip flash memory with ECC and Read While Write (RWW) - 192 KB on-chip RAM with standby functionality (32 KB) and ECC - 8 KB instruction cache (with line locking), configurable as 2- or 4-way - 14 + 3 KB e TPU code and data RAM - 5  4 crossbar switch (XBAR) - 24-entry MMU - External Bus Interface (EBI) with slave and master port - Fail Safe Protection - 16-entry Memory Protection Unit (MPU) - CRC unit with 3 sub-modules - Junction temperature sensor - Interrupts - Configurable interrupt controller (with NMI) - 64-channel DMA - Serial channels - 3  e SCI - 3  DSPI (2 of which support downstream Micro Second Channel [MSC]) Table 1. Device summary LBGA208 PBGA324 LQFP176 - 3  Flex CAN with 64 messages each - 1  Flex Ray module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC - 1  e MIOS - 1  e TPU2 (second generation e TPU) - 2 enhanced queued analog-to-digital converters (e QADCs) - On-chip CAN/SCI/Flex Ray Bootstrap loader with Boot Assist Module (BAM) - Nexus: Class 3+ for core; Class 1 for the e TPU - JTAG (5-pin) - Development Trigger Semaphore (DTS) - Clock generation - On-chip 4- 40 MHz main oscillator - On-chip FMPLL (frequency-modulated phase-locked...