SPC564L70L3 Datasheet PDF

FEATURES

● High-performance e200z4d dual core – 32-bit Power Architecture® technology CPU – Core frequency as high as 120 MHz – Dual issue five-stage pipeline core – Variable Length Encoding (VLE) – Memory Management Unit (MMU) – 4 KB instruction cache with error detection code – Signal Processing Engine (SPE)
● Memory available – 2 MB flash memory with ECC – 192 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM emulation
● SIL3/ASILD innovative safety concept: Lock step mode and Fail-safe protection – Sphere of Replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) – Fault Collection and Control Unit (FCCU) – Redundancy Control and Checker Unit (RCCU) on outputs of the SoR connected to FCCU – Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware – Boot-time Built-In Self-Test for ADC and flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non Maskable...