Datasheet4U Logo Datasheet4U.com

SPC56AP60L5 - 32-bit MCU

This page provides the datasheet information for the SPC56AP60L5, a member of the SPC560P54L5 32-bit MCU family.

Description

.

.

.

.

.

.

.

Features

  • AEC-Q10x qualified.
  • 64 MHz, single issue, 32-bit CPU core complex (e200z0h).
  • Compliant with Power Architecture® embedded category.
  • Variable Length Encoding (VLE).
  • Memory organization.
  • Up to 1024 KB on-chip code Flash memory with additional 64 KB for EEPROM emulation (data flash), with ECC, with erase/program controller.
  • Up to 80 KB on-chip SRAM with ECC.
  • Fail safe protection.
  • ECC protection on system SRAM and Flash.
  • Safet.

📥 Download Datasheet

Datasheet preview – SPC56AP60L5

📁 Similar Datasheet

  • SPC5604 - N & P Pair Enhancement Mode MOSFET (SYNC POWER)
  • SPC5606S - Microcontroller (Freescale Semiconductor)
  • SPC560B40L1 - 32-bit MCU (ST Microelectronics)
  • SPC560B40L3 - 32-bit MCU (ST Microelectronics)
  • SPC560B40L5 - 32-bit MCU (ST Microelectronics)
  • SPC560B44L3 - 32-bit MCU family built on the Power Architecture embedded category (ST Microelectronics)
  • SPC560B44L5 - 32-bit MCU family built on the Power Architecture embedded category (ST Microelectronics)
  • SPC560B50B2 - 32-bit MCU family built on the Power Architecture embedded category (ST Microelectronics)
  • SPC560B50L1 - 32-bit MCU (ST Microelectronics)
  • SPC560B50L3 - 32-bit MCU (ST Microelectronics)
Other Datasheets by STMicroelectronics

Full PDF Text Transcription

Click to expand full text
SPC56AP60x, SPC56AP54x SPC560P60x, SPC560P54x 32-bit Power Architecture® based MCU with 1088KB Flash memory and 80KB RAM for automotive chassis and safety applications Datasheet - production data LQFP100 14 x 14 mm LQFP144 20 x 20 mm Features  AEC-Q10x qualified  64 MHz, single issue, 32-bit CPU core complex (e200z0h) – Compliant with Power Architecture® embedded category – Variable Length Encoding (VLE)  Memory organization – Up to 1024 KB on-chip code Flash memory with additional 64 KB for EEPROM emulation (data flash), with ECC, with erase/program controller – Up to 80 KB on-chip SRAM with ECC  Fail safe protection – ECC protection on system SRAM and Flash – Safety port – SWT with servicing sequence pseudorandom generator – Power management – Non-maskable interrupt for both cores
Published: |