SPC582B54E3 Datasheet PDF

FEATURES

● AEC-Q100 qualified
● High performance e200z2 single core – 32-bit power architecture technology CPU – Core frequency as high as 80 MHz – Variable length encoding (VLE) – Floating point, End-to-End error correction
● 1088 KB (1024 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
● 96 KB on-chip general-purpose SRAM
● Multi-channel direct memory access controller (eDMA) with 16 channels
● 1 interrupt controller (INTC)
● Comprehensive new generation ASIL-B safety concept – ASIL-B of ISO 26262 – FCCU for collection and reaction to failure notifications – Memory error management Unit (MEMU) for collection and reporting of error events in memories – Cyclic redundancy check (CRC) unit – End-to-end error correction code (e2eECC) logic
● Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters with end-to-end ECC
● Body cross trigge...