SPC58NH84E7 Datasheet | STMicroelectronics

Features - AEC-Q100 qualified - High performance e200z4 triple core: - 32-bit Power Architecture technology CPU - Core frequency as high as 200 MHz - Variable Length Encoding (VLE) - Floating Point, End-to-End Error Correction - 10496 KB (10240 KB code Flash + 256 KB data Flash) on-chip Flash memory: - Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation - Supports read while read between the two code Flash partitions - Hardware support for Flash context switching (for FOTA with multi software versions) - 1088 KB on-chip general-purpose SRAM (in addition to 192 KB core local data RAM): - 64 KB in CPU_0, 64 KB in CPU_1 and 64 KB in CPU_2 - 224 KB HSM dedicated Flash memory (192 KB code + 32 KB data) - Multi-channel direct memory access controller (e DMA): - One e DMA with 64 channels - One e DMA with 16 channels - One interrupt controller (INTC) - prehensive new generation ASIL-D safety concept: - ASIL-D of ISO 26262 - One CPU channel in lockstep - Logic BIST - FCCU for collection and reaction to failure notifications - Memory BIST - Cyclic redundancy check (CRC) unit - Memory Error Management Unit (MEMU) for collection and reporting of error events in memories - Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC - Body cross triggering unit (BCTU): - Triggers ADC conversions from any e MIOS channel - Triggers ADC conversions from up to 2 dedicated PIT_RTIs - Enhanced modular IO subsystem (e MIOS): - up to 96 timed IO channels with 16-bit counter resolution - Enhanced analog-to-digital converter system with: - 4 independent fast 12-bit SAR analog converters - One supervisor 12-bit SAR analog converter - One standby 10-bit SAR analog converter - 100 ADC channels - munication interfaces: - 24 LINFlex D modules - 10 deserial serial peripheral interface (DSPI)...