STMicroelectronics SSM1105V
The SSM1105V devices feature a dual -bank flash architecture, Dual Display Data Channels (DDC), I2C, PWM channels, general purpose I/O, programmable logic, and in-system programming via either JTAG or I2C. The dual-bank Flash memory architecture supports full concurrent operation permitting IAP in the field, which means that firmware can be remotely updated with little interruption of system operation.
| Part No. |
SSM1105V |
| Datasheet |
SSM1105V
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| Manufacturer |
 STMicroelectronics |
| Description |
Scalar System Memory SSM |
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FEATURES
SUMMARY s System solution for use with image processing scalar ICs – For LCD monitors, projectors, and TVs – Compatible with Pixelworks PW11x/PWx64 families (and similar image processors or micro-controllers) s decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM Figure 1. Packages Single integrated package, including: – Dual bank Flash memories – DDC, I2C, and PWM channels – General purpose I/O – Programmable logic – In-System Programming via JTAG s Dual bank Flash memories – Provide concurrent operation – 5 Mbit main Flash memory – 384 Kbit secondary Flash memory (divided into 10 small sectors) – Programmable Decode PLD for flexible address mapping of both memories TQFP100 (U) s Dual Display Data Channels (DDC) – Supports DDC for both analog RGB and digital DVI video input channels – DDC1/DDC2B VESA standard compliant – 256 byte SRAM buffer for each DDC channel s In-System Programming (ISP) with JTAG – Program entire chip in 30-40 seconds with n...
