SSM1105V Datasheet | STMicroelectronics

FEATURES SUMMARY s System solution for use with image processing scalar ICs - For LCD monitors, projectors, and TVs - patible with Pixelworks PW11x/PWx64 families (and similar image processors or micro-controllers) s decoders, chip-selects, inverters; and to prioritize interrupts from DDC, I2C, PWM Figure 1. Packages Single integrated package, including: - Dual bank Flash memories - DDC, I2C, and PWM channels - General purpose I/O - Programmable logic - In-System Programming via JTAG s Dual bank Flash memories - Provide concurrent operation - 5 Mbit main Flash memory - 384 Kbit secondary Flash memory (divided into 10 small sectors) - Programmable Decode PLD for flexible address mapping of both memories TQFP100 (U) s Dual Display Data Channels (DDC) - Supports DDC for both analog RGB and digital DVI video input channels - DDC1/DDC2B VESA standard pliant - 256 byte SRAM buffer for each DDC channel s In-System Programming (ISP) with JTAG - Program entire chip in 30-40 seconds with no involvement of the processor - Program with low-cost Flash LINK s Dual independent I2C channels - Each capable of master or slave operation - Control A/D converters, video decoders, and future devices (tuner, audio, etc.) s Content Security: Programmable Security Bit blocks access of device programmers / readers Zero-Power Technology: memory and PLD blocks automatically switch to stand-by current between input changes Package and Specifications - 100-pin TQFP, 14 x 14mm - 90 ns memory access time - VCC Operating Voltage: 2.7V to 3.6V s Four Pulse Width Modulator (PWM) channels - 16-bit resolution for period and for duty cycle - 16-bit clock prescalers s s Seven I/O ports with 52 I/O pins for Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, and JTAG 3000 gate PLD with 16 macrocells, for creating glue logic, state machines, clock dividers, s s November 2002 This is information on a product still in production but not remended for new designs. 1/4 .. SUMMARY...