ST10F271 Datasheet PDF

FEATURES

● 16-bit CPU with DSP functions – 31.25ns instruction cycle time at 64MHz max CPU clock – Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support On-chip memories – 128 Kbyte Flash memory (32-bit fetch) – Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles. – Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I2C) – 2 Kbyte internal RAM (IRAM) – 10 Kbyte extension RAM (XRAM) – Programmable external bus configuration & characteristics for different address ranges – Five programmable chip-select signals – Hold-acknowledge bus arbitration support Interrupt – 8-channel peripheral event controller for single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns Timers – Two multi-functional general purpose timer units with 5 timers Two 16-channel capt...