ST10F280 Datasheet PDF

FEATURES

● High performance cpu with dsp functions – 16-bit CPU with 4-stage pipeline. – 50ns Instruction cycle time at 40MHz CPU clock – Multiply/accumulate unit (MAC) 16 x 16-bit multiplication, 40-bit accumulator – Repeat unit – Enhanced boolean bit manipulation facilities – Additional instructions to support hll and operating systems – Single-cycle context switching support
● Memory organization – 512KB on-chip Flash memory single voltage with erase/program controller – 100K erasing/programming cycles – 20 year data retention time – Up to 16MB linear address space for code and data (5MB with CAN) – 2KB on-chip internal ram (IRAM) – 16KB extension RAM (XRAM)
● Fast and flexible bus – Programmable external bus characteristics for different address ranges – 8-bit or 16-bit external data bus – Multiplexed or demultiplexed external address/data buses – Five programmable chip-select signals – Hold-acknowledge bus arbitration support
● Interrupt – 8-channel peripheral event controller for...