FEATURES
INCLUDING EEPROM FLASH ERASE CONTACT ASSIGNMENT COMPATIBLE ISO 7816-2 s Function 512 bits signature with CRT ** 512 bits signature without CRT 768 bits signature with CRT 768 bits authentication (e=$10001) 1024 bits signature with CRT 1024 bits authentication (e=$10001) Note * 5MHz clock CPU ** CRT: Chinese Remainder Theorem s BD.CF54-B/9809V2 This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29 1/3 1 ST16CF54 Level B DESCRIPTION
By using of software (cryptographic firmware library) this calculation can be extended for any size of operand from 3 to 1024 bits. The ST16CF54 Level B is based on an ST 8 bit CPU core including on-chip memories: 512 Bytes of RAM, 16 KBytes of USER ROM and 4 KBytes of EEPROM. Both ROM and EEPROM memories can be configured into two sectors. Access rules from any memory section (sector) to another are setup by the User defined Memory Access Control Matrix.